module Decoder(
        input wire [1:0] inputs,
        output reg [3:0] outputs
    );
        always @(*)
            case (inputs)
                2'b00: outputs = 4'b0001;
                2'b01: outputs = 4'b0010;
                2'b10: outputs = 4'b0100;
                2'b11: outputs = 4'b1000;
                default: outputs = 4'b0000;
            endcase
    endmodule
